Invention Reference Number
Stacked die in power electronics refers to a packaging approach where multiple semiconductor dies are vertically integrated or "stacked" in a single package. This technique aims to reduce the loop inductance and volume of power electronic systems but increases heat extraction challenges. Such die stacking technique introduces heat loading from one die to another and additional layers in between the devices increases effective thermal resistance. With highly resistive path between junction to case the traditional cooling systems will not be adequate to keep the device temperature within manufacturers recommended limits unless the device rating is significantly reduced. To overcome the thermal challenges, a novel stack design has been proposed along with cooling system that can match the thermal performance of the traditional packaging techniques with added benefit of low power loop inductance and high density.
Contact
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